ICCS 2025
Special Session on Chiplet-based Integrated Systems
基于芯粒的集成系统
Chip vendors face significant challenges with the continued slowing down of Moore’s Law and the end of Dennard scaling which increases the time between new technology nodes and thus skyrockets manufacturing costs for silicon. The slowing down of Moore’s Law makes it increasingly difficult to integrate more transistors on a single chip. If transistor sizes stay constant, more transistors could be integrated via larger chips. However, larger chips are undesirable due to significantly higher manufacturing and verification costs. Manufacturing defects in high density integrated circuits can dramatically reduce the wafer yield. Lower yield translates into higher manufacturing cost. 随着摩尔定律的持续放缓和丹纳德缩放定律失效，芯片供应商面临着重大挑战。新技术节点之间演进的时间大大增加，从而使硅芯片的制造成本飙升。摩尔定律的放缓使单个芯片上集成更多晶体管变得越来越困难。如果晶体管尺寸保持不变，则只能用更大的芯片去集成更多的晶体管。然而，由于制造和验证成本显着增加，制造较大的芯片是不可取的。高密度集成电路中的制造缺陷会显着降低晶圆产量，而较低的产量会推高的制造成本。 Papers can be submitted via online system. The confirmation e-mail from the conference staff will be sent out within two working days. 如您有意向投稿，请点击线上投递论文。我们的工作人员将在收到稿件的两个工作日内反馈文章编号，请注意查收。 Letian Huang, University of Electronic Science and Technology of China Xiaohang Wang, Zhejiang University Bio: Dr. Letian Huang received the MS and Ph. D. degrees in communication and information system from the University of Electronic Science and Technology of China (UESTC), Chengdu, China in 2009 and 2016, respectively. He is an associate professor with UESTC. His scientific work contains more than 40 publications including book chapters, journal articles and conference papers. He is the IEEE CEDA Chengdu Chapter Chair. He was the general chair of ICCS 2020 and 2021, TPC co-chair of ICITES 2021, and TPC Chair of ICICM2020 2021. He also served as the guest editor of the Microelectronics Journal. His research interests include heterogeneous multi-core system-on-chips, networkon-chips, and mixed signal IC design. Bio: Dr. Xiaohang Wang received the B. Eng. and Ph. D. degree in communication and electronic engineering from Zhejiang University, in 2006 and 2011, respectively. He is currently an associate professor at South China University of Technology. He was the receipt of PDP 2015 and VLSI-SoC 2014 Best Paper Awards. He was the special session chair of NoCS 2018, co-organizer of NoCArc 2014-2018, and TPC chair of ICCS 2021. He also served as the guest editor of the Microelectronics Journal. His research interests include many-core architecture, power efficient architectures, optimal control, and NoC-based systems.
As a promising design paradigm to solve the above challenge, in chiplet-based systems, multiple die/chiplets are integrated within the same package via advanced packaging technology such as a multi-chip module or silicon interposer. The chiplet architectures provide a variety of benefits that make them attractive, including lower cost, higher flexibility, and better sustainability. However, the design methodology should be studied to support efficient design of chiplet-based systems. In this special session, we will focus on the challenges of chiplet-based integrated systems and innovations to address these challenges. Topics for this session include but not limited to: 在基于芯粒的系统中是解决上述挑战的技术途径中有前途的一种，它是指多个裸芯/芯粒通过先进的封装技术（如多芯片模组或硅中介层）集成在同一封装中。基于芯粒的架构提供了多种优势，包括成本更低、灵活性更高和可持续性更好。但是现在仍应该研究更为高效的设计方法来设计基于芯粒的系统。在本次特别会议中，我们将重点关注基于芯粒的集成系统的挑战以及应对这些挑战的创新。本次会议的主题包括但不限于：
Paper Submission
Organizers
黄乐天, 电子科技大学
王小航，浙江大学