Assistant Professor, AMSV and IME/FST-ECE, University of Macau, China
Yong Chen received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.
From 2010 to 2013, He worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016.
His research interests include integrated circuit designs involving analog/mixed-signal/RF/mm-wave/sub-THz/wireline.
Dr. Chen was the co-recipient of the Best Paper Award at the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2019. His team reported 2 chip inventions at the 2019 IEEE International Solid-State Circuits Conference - ISSCC (Chip Olympics): mm-wave PLL (‘19) and VCO (‘19).
Dr. Chen serves as an Associate Editor of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems since 2019, an Associate Editor of IEEE Access since 2019 and an Editor of International Journal of Circuit Theory and Applications (IJCTA) since 2020. He services a Vice-Chair of IEEE Macau CAS Chapter (’19-‘20), a conference local organization committee of A-SSCC (’19) and a member of Technical Program Committee of APCCAS (‘19), ICTA ('20) and ICSICT ('20).